市民在丹轩梓园买新房 进户水管爆裂刚装修好房子被淹
| General information | |
|---|---|
| Launched | 2021 |
| Designed by | ARM Ltd. |
| Cache | |
| L1 cache | 64/128 KiB (32/64 KiB I-cache with parity, 32/64 KiB D-cache) per core |
| L2 cache | 256/512 KiB per core |
| L3 cache | 256 KiB – 16 MiB (optional) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-A710 |
| Instruction set | ARMv9.0-A |
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Predecessor | ARM Cortex-A78 |
| Successor | ARM Cortex-A715 |
The ARM Cortex-A710 is the successor to the ARM Cortex-A78, being the First-Generation Armv9 "big" Cortex CPU.[1] It is the companion to the ARM Cortex-A510 "LITTLE" efficiency core. It was designed by ARM Ltd.'s Austin centre.[2] It is the fourth and last iteration of Arm's Austin core family.[2]
It forms part of Arm's Total Compute Solutions 2021 (TCS21) along with Arm's Cortex-X2, Cortex-A510, Mali-G710 and CoreLink CI-700/NI-700.[3]
Architecture changes in comparison with ARM Cortex-A78
[edit]The processor implements the following changes:[2]
- Rename / Dispatch width: 5 (decreased from 6).
- 10-cycle pipeline (decreased from 11).
- One of only two ARMv9 cores to support EL0 AArch32, along with the ARM Cortex-A510.
Improvements:
- 30% more power efficient than Cortex-A78.
- 10% uplift in performance compared to Cortex-A78[4]
- 2x ML uplift[1]
Architecture comparison
[edit]- "big" core
| μArch | Cortex-A77 | Cortex-A78 | Cortex-A710 | Cortex-A715 | Cortex-A720 | Cortex-A725 |
|---|---|---|---|---|---|---|
| Codename | Deimos | Hercules | Matterhorn | Makalu | Hunter | Chaberton |
| Peak clock speed | 2.6 GHz | ~3.0 GHz | - | |||
| Architecture | ARMv8.2-A | ARMv9.0-A | ARMv9.2-A | |||
| AArch | - | 32-bit and 64-bit | 64-bit | |||
| Max In-flight | 160 | 160 | ? | 192+ [5] | ? | - |
| L0 (Mops entries) | - | 1536 [6] | 0 [7] | - | ||
| L1 (I + D) (KiB) | 64 + 64 KiB | 32/64 + 32/64 KiB | 64 + 64 KiB | |||
| L2 Cache (KiB) | 256–512 KiB | 128–512 KiB | 0.25–1 MiB [8] | |||
| L3 Cache (MiB) | 0–4 MiB | 0–8 MiB | 0–16 MiB | 0–32 MiB [9] | ||
| Decode width | 4-way | 5-way | ||||
| Dispatch | 6 Mops/cycle | 5 Mops/cycle [10] | ? | - | ||
Usage
[edit]- MediaTek Dimensity 9000/9000+[14]
- Samsung Exynos 2200[15]
See also
[edit]- ARM Cortex-X2, related high performance microarchitecture
- Comparison of ARMv8-A cores, ARMv8 family
References
[edit]- ^ a b "First Armv9 Cortex CPUs for Consumer Compute". community.arm.com. Retrieved 2025-08-04.
- ^ a b c "Arm Announces Mobile Armv9 CPU Microarchitectures: Cortex-X2, Cortex-A710 & Cortex-A510". www.anandtech.com. Retrieved 2025-08-04.
- ^ "Arm Total Compute solutions powering decade of compute - Architectures and Processors blog - Arm Community blogs - Arm Community". community.arm.com. 2025-08-04. Retrieved 2025-08-04.
- ^ Ltd, Arm. "Cortex-A710". Arm | The Architecture for the Digital World. Retrieved 2025-08-04.
- ^ "Arm Introduces The Cortex-A715". WikiChip Fuse. 2025-08-04. Retrieved 2025-08-04.
- ^ "Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence". www.anandtech.com. Retrieved 2025-08-04.
- ^ "Documentation – Arm Developer". developer.arm.com. Retrieved 2025-08-04.
- ^ "Arm launches next gen big core Cortex-A725". WikiChip Fuse. 2025-08-04.
- ^ "Arm introduces a new big core Cortex-A720". WikiChip Fuse. 2025-08-04.
- ^ "Arm Cortex-X2, A710, and A510 deep dive: New Armv9 CPU designs explained". Android Authority. 2025-08-04. Retrieved 2025-08-04.
- ^ "Snapdragon 7 Gen 1 Mobile Platform | Qualcomm". www.qualcomm.com. Retrieved 2025-08-04.
- ^ "Snapdragon 7+ Gen 2 Mobile Platform". Qualcomm. Retrieved 17 March 2023.
- ^ "Qualcomm Snapdragon 8 Gen 1 Mobile Platform | Latest 5G Snapdragon Processor | Qualcomm". www.qualcomm.com. Retrieved 2025-08-04.
- ^ "MediaTek | MediaTek Dimensity 9000". www.mediatek.com. Retrieved 2025-08-04.
- ^ "Exynos 2200 Mobile Processor". semiconductor.samsung.com. Retrieved 2025-08-04.